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matteo porta 2022-09-13 13:14:24 +02:00
parent 390b93242b
commit 39820e6604
1 changed files with 4 additions and 2 deletions
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6
src/ui/test_resistance/test_resistance.py
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@ -16,6 +16,9 @@ class Test_Resistance(Test_Test):
else:
self.simulate = False
# /TESTING
expected = step.spec.get("expected", "-")
if expected == float("+inf"):
step.spec["expected"] = 1e9
super().start(recipe=recipe, step=step)
if self.run_once is True and self.done is True and self.done_ok is True:
return
@ -24,8 +27,7 @@ class Test_Resistance(Test_Test):
self.get_connection = self.components["multicomp"].out.connect(self.get)
self.components["multicomp"].resume()
expected = self.step.spec.get("expected", "-")
if expected == float("+inf"):
self.step.spec["expected"] = 1e9
if expected == 1e9:
self.ok_counter_limit = 1
self.parent_assembly_widget().set_text(u"SCOLLEGARE IL CONNETTORE")
else: